1. Field of the Invention
The invention relates to a delay device comprising storage elements arranged in at least two rows in an integrated circuit, preferably in switched-capacitor technology.
2. Description of the Related Art
European Patent Application EP-A-0 383 387, corresponding to U.S. Pat. No. 5,012,143 discloses an integrated circuit which includes delay devices whose storage elements are implemented in switched-capacitor technology and which are arranged in a plurality of rows. In such delay devices having their storage elements arranged in a plurality of rows, a problem arises when the delay devices should produce a delay by an odd multiple of the clock period with which the signals stored temporarily in the storage elements are read out. This is because during read-out (as well as during read in,) the clock signal should alternately be applied to the rows of storage elements, in which the rows should each have the same number of storage elements. Therefore, in the case of, for example, a delay device having storage elements arranged in two rows, a delay by an odd multiple of the period of the clock signal for read-in and read-out cannot readily be obtained.